Lab 8 - ECE 421L 

 

Generating a test chip layout for submission to MOSIS for fabrication.

                                                                                        

Group: Lizz Heider, Moriah Wingrove, Cody Jones

 

Pre-Lab Description

Back up all previous work

Tutorial 6 – process of design and layout of a padframe for fabrication.

Below we show padframe schematic, symbol, and layout:

 

 

 

 

Lab Description

 

Chip must include the following

·        One or more course projects

·        A 31-staged ring oscillator with a buffer for diving a 20pF off-chip load

·        NAND and NOR gates using 6/0.6u NMOS & PMOS

·        An inverter made with a 6/0.6u NMOS and a 12/0.6u PMOS

·        Transistors, both PMOS and NMOS, measuring 6u/0.6u where all 4 terminals of each device are connected to bond pads (7 pads + common gnd pad) 

o   Note that only one pad is needed for the common gnd pad. This pad is used to ground the p-substrate and provide ground to each test circuit

·        Using the 25k resistor laid out below and a 10k resistor implement a voltage divider (need only 1 more pad above the ones used for the 25k resistor) 

·        A 25k resistor implemented using the n-well (connect between 2 pads but we also need a common gnd pad)   

 

 

PIN<1:20>

 

Labels

 

Pin<21:40>

 

Labels

PIN 1

Output V_div

PIN 21

 

PIN 2

Drain NMOS

PIN 22

 

PIN 3

Gate of NMOS

PIN 23

 

PIN 4

Source NMOS (BODY TO GND)

PIN 24

Input A INVERTER

PIN 5

Gate of PMOS

PIN 25

Output Anot INVERTER

PIN 6

Drain PMOS

PIN 26

VDD INVERTER

PIN 7

VDD PMOS

PIN 27

Input NAND A

PIN 8

Source of PMOS

PIN 28

VDD NAND

PIN 9

 

PIN 29

Input B NAND

PIN 10

 

PIN 30

Input A NOR

PIN 11

 

PIN 31

Input B NOR

PIN 12

 

PIN 32

VDD NOR

PIN 13

 

PIN 33

Output NOR AnorB

PIN 14

 

PIN 34

VDD ring oscillator and buffer

PIN 15

 

PIN 35

Output of oscillator

PIN 16

 

PIN 36

 

PIN 17

VDD Boost SPS

PIN 37

 

PIN 18

Input Boost SPS

PIN 38

 

PIN 19

Vout Boost SPS

PIN 39

NAND Out

PIN 20

GND

PIN 40

Input V_div


CHIP DESIGN SCHEMATIC

 

 

CHIP DESIGN LAYOUT

 

 

4-Terminal NMOS

4-T-Nmos is connected to pins 2,3,4 (body pin connected to common gnd on padframe)
To test the chip, supply gate voltage to pin 3, drain voltage to pin 2, and source voltage to pin 4.

 

 

4-Terminal PMOS

4-T-PMOS connected to pins 5,6,7,8.

Test chip- supply gate voltage to pin5, drain voltage to pin6, source voltage to pin7, and ground pin20
(common ground).

 

NAND Gate

NAND gate connects to pins 27,28, 29, 39 on the padframe.

 

Testing the chip, connect pin 28 for the VDD of the circuit, pins 27 and 29 for the inputs, and pin 39 for the output.

 

NOR GATE

NOR gate connects to pins 30-33 on the padframe

Testing the chip, connect pin 32 to Vdd, pin30 and pin31 used for the inputs, and pin33 is connected to the output.
Ground is common ground.

 

 

31-Stage Ring Oscillator

 

 

Voltage Divider

 

Testing the chip involves supplying the input of the voltage divider on pin 40,

the output of the divider on pin 1, and the ground to the common ground on pin 20

 

Inverter

Inverter connects to pins 24-26.

To test the chip we supply VDD to pin26, input of the inverter to pin24, and output of the inverter to pin25.

 

 

 

Boost SPS – Cody

Connects to pins 17-19

To test this chip we supply

 

 

Test Chip Layout

 

The layout passes DRC and LVS

   

 

Link to Lab directory here

 

 

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